View ISL6560_705013.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(R)
ISL6560
Data Sheet October 22, 2004 FN9011.3
Microprocessor CORE Voltage Regulator Two-Phase Buck PWM Controller
The ISL6560 two-phase current mode, PWM control IC together with companion gate drivers, the HIP6601A, HIP6602A, HIP6603A or HIP6604 and MOSFETs provides a precision voltage regulation system for advanced microprocessors. Two-phase power conversion is a marked departure from earlier single phase converter configurations previously employed to satisfy the ever increasing current demands of modern microprocessors. Multi-phase converters, by distributing the power and load current, results in smaller and lower cost transistors with fewer input and output capacitors. These reductions accrue from the higher effective conversion frequency with higher frequency ripple current due to the phase interleaving process of this topology. For example, a two phase converter operating at 350kHz per phase will have a ripple frequency of 700kHz. Higher converter bandwidth is also achievable, resulting in faster response to load transients. An outstanding feature of this controller IC includes highside current sensing with a single current sampling resistor in the input line to the output MOSFET transistors. This single current sampling resistor monitors each channels input current assuring excellent current sharing. Current mode control results in rapid response to changing load demands. Also featured are programmable VID codes with an accuracy of 0.8% that range from 1.100-1.850V, and are set by the microprocessor. Pull up currents on these VID pins eliminates the need for external pull-up resistors. Another feature of this controller IC is the PWRGD monitor circuit and load protection circuits which provide overvoltage protection, overcurrent protection and undervoltage indication.
Features
* Two-phase power conversion * Precision channel current sharing * Precision CORE voltage regulation - 0.8% accuracy * Microprocessor voltage identification input - VRM 9.0 compliant - 5-bit VID input - 1.100 to 1.850V in 25mV steps - Programmable "droop" voltage * Fast transient recovery time * Overcurrent protection * High output ripple frequency. . . . . . . . . . . . . 100kHz to 2MHz * Pb-Free Available (RoHS Compliant)
Applications
* VRM9.X modules * AMD AthlonTM processor voltage regulator * Low output voltage, high current DC/DC converters
Related Literature
* Technical Brief TB363 Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)
Pinout
ISL6560 (SOIC) TOP VIEW
VID4 1 VID3 2 VID2 3 VID1 4 16 VCC 15 REF 14 CS13 PWM1 12 PWM2 11 CS+ 10 PWRGD 9 GND
Ordering Information
PART NUMBER ISL6560CB ISL6560CB-T ISL6560CBZ (See Note) ISL6560CBZ-T (See Note) ISL6560/62EVAL1 TEMP. (C) 0 to 70 0 to 70 PACKAGE 16 Ld SOIC 16 Ld SOIC (Pb-free) PKG. DWG.# M16.15 M16.15
VID0 5 COMP 6 FB 7 CT 8
16 Ld SOIC Tape and Reel
16 Ld SOIC Tape and Reel (Pb-free) Evaluation Platform
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc. AthlonTM is a trademark of Advanced Micro Devices, Inc. | Copyright (c) Intersil Americas Inc. 2003, 2004, All Rights Reserved
ISL6560 Block Diagram
REF VCC
3V REFERENCE PWRGD
UVLO and BIAS CIRCUITS OSCILLATOR CT PWM1 CONTROL LOGIC PWM2 CMP
+ X 0.82
UV
+ X1.24 VID4 VID3 VID2 VID1 VID0 FB COMP D/A E/A +
-
OVP
+
CS+ CS-
-
-
GND
Simplified Power System Diagram
FB PWM 1 SYNCHRONOUS RECTIFIED BUCK CHANNEL MICROPROCESSOR PWM 2 SYNCHRONOUS RECTIFIED BUCK CHANNEL
sense comparator. Pulling this pin to ground disables the oscillator and drives both PWM outputs low.
FB (Pin 7)
Inverting input of the internal transconductance error amplifier.
ISL6560
CT (Pin 8)
A capacitor on this pin sets the frequency of the internal oscillator.
VID
Functional Pin Description
VID4 1 VID3 2 VID2 3 VID1 4 VID0 5 COMP 6 FB 7 CT 8 16 VCC 15 REF 14 CS13 PWM1 12 PWM2 11 CS+ 10 PWRGD 9 GND
GND (Pin 9)
All signals are referenced to this bias and reference ground pin.
PWRGD (Pin 10)
This pin is an internal open drain connection. A high voltage level at this pin with a resistor connected to this pin and VCC indicates that CORE voltage is at the proper level,
CS+ (Pin 11) and CS- (Pin 14)
These inputs monitor the supply current to the upper MOSFETs. CS+ is connected directly to the decoupled supply voltage and current sensing resistor. CS- is connected to the other end of the current sensing resistor and the upper MOSFET drains.
VID4 (Pin 1), VID3 (Pin 2), VID2 (Pin 3), VID1 (Pin 4) and VID0 (Pin 5)
Voltage Identification inputs from microprocessor. These pins respond to TTL and 3.3V logic signals. The ISL6560 decodes VID bits to establish the output voltage. See Table 1.
PWM2 (Pin 12) and PWM1 (Pin 13)
PWM outputs that are connected to the gate driver ICs.
REF (Pin 15)
Three volt supply used to bias the output of the transconductance amplifier.
COMP (Pin 6)
Output of the internal transconductance error amplifier. Voltage at this pin sets the output current level of the current
VCC (Pin 16)
Connect this bias supply pin to a 12V supply.
2
FN9011.3
ISL6560
Absolute Maximum Ratings
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 15V CS+. CS- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V PWRGD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC All Other Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5V ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV
Thermal Information
Thermal Resistance (Note 1) JA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC - Lead Tips Only)
Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC Maximum Operating Junction Temperature . . . . . . . . . . . . . . 125oC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V 10%
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
PARAMETER VCC SUPPLY CURRENT Input Supply Current Input Supply Current, UVLO Mode Undervoltage Lock Out Voltage Undervoltage Lock Out Hysteresis
Recommended Operating Conditions, Unless Otherwise Noted SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
ICC ICC(UVLO) VUVLO
VCC = 12V VCC VUVLO, VCC Rising
5.4 0.1
5.8 5.7 6.4 0.4
9.0 8.9 6.9 0.8
mA mA V V
DAC and REFERENCE VOLTAGES Minimum DAC Programed Voltage Middle DAC Programed Voltage Maximum DAC Programed Voltage Line Regulation Crowbar Trip Point at FB Input Crowbar Reset Point at FB Input Crowbar Response Time Reference Voltage Output Current VID INPUTS Input Low Voltage Input High Voltage VID Pull-Up Internal Pull-Up Voltage OSCILLATOR Maximum Frequency Frequency Variation CT Charging Current CT Charging Current ERROR AMPLIFIER Output Resistance Transconductance Output Current RO(ERR) gm(ERR) Io(ERR) FB Forced to VOUT - 3% 2.0 200 2.2 1 2.4 k mS mA fCT(MAX) fCT ICT ICT TA = 25oC, CT = 91pF TA = 25oC, VFB in Regulation TA = 25oC, VFB = 0V 2.0 430 130 26 500 150 36 570 170 46 MHz kHz A A VIL(VID) VIH(VID) IVID VIDx = 0V or VIDx = 3V 2.2 10 4.5 20 5.0 0.6 40 5.5 V V A V VFB VFB VFB VFB VCROWBAR VCROWBAR ICROWBAR VREF IREF DAC Programmed to 1.100V DAC Programmed to 1.475V DAC Programmed to 1.850V VCC = 10V to 14V Percent of Nominal DAC Voltage Percent of Nominal DAC Voltage Overvoltage to PWM Going Low 0mA IREF 1mA 1.091 1.463 1.835 114 50 2.952 1 1.100 1.475 1.850 0.05 124 60 300 3.000 3 1.109 1.487 1.865 134 70 3.048 V V V % % % ns V mA
3
FN9011.3
ISL6560
Electrical Specifications
PARAMETER Input Bias Current Maximum Output Voltage Output Disable Threshold FB Low Foldback Threshold -3dB Bandwidth CURRENT SENSE Threshold Voltage VCS(TH) CS+ = VCC, FB Forced to VOUT - 3% 0.8 COMP 1V Current Limit Foldback Voltage VCOMP/VCS Input Bias Current Response Time POWER GOOD COMPARATOR Undervoltage Threshold Overvoltage Threshold Output Voltage Low Response Time Response Time PWM OUTPUTS Output Voltage Low Output Voltage High Output Current Duty Cycle Limit, by Design
.
Recommended Operating Conditions, Unless Otherwise Noted SYMBOL IFB VCOMP(MAX) FB Forced to VOUT - 3% VCOMP(OFF) VFB(LOW) BWERR COMP = Open TEST CONDITIONS MIN 560 375 TYP 5 3.0 720 425 500 MAX 100 800 500 UNITS nA V mV mV kHz
142 75 -
157 0 95 12.5 0.5 50
172 15 115 5.0 -
mV mV mV V/V A ns
VCS(FOLD) ni ICS+, ICStCS
FB 375mV 1 V VCOMP 3V CS+ = CS- = VCC CS+ - (CS-) 172mV to PWM Going Low
VPWRGD(UV) Percent of Nominal Output VPWRGD(OV) Percent of Nominal Output VOL(PWRGD) IPWRGD(SINK) = 100A FB Going High FB Going Low
76 114 -
82 124 30 2 200
88 134 200 -
% % mV s ns
VOL(PWM) VOH(PWM) IPWM DMAX
IPWM(SINK) = 400A IPWM(SOURCE) = 400A
4.5 0.4
100 5.0 1 -
500 5.5 50
mV V mA %
Per Phase, Relative to fCT
-
TABLE 1. VOLTAGE IDENTIFICATION CODES VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 VDAC Off 1.100 1.125 1.150 1.175 1.200 1.225 1.250 1.275 1.300 1.325 1.350 1.375 1.400 1.425 1.450 1.475 1.500
TABLE 1. VOLTAGE IDENTIFICATION CODES (Continued) VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 VDAC 1.525 1.550 1.575 1.600 1.625 1.650 1.675 1.700 1.725 1.750 1.775 1.800 1.825 1.850
4
FN9011.3
ISL6560
5
FN9011.3
ISL6560 General Circuit Description
RSENSE INPUT VOLTAGE GATE DRIVER and OUTPUT FETs CS-
CS+
ISL6560
+Current Comparator OUTPUT GATE DRIVERS and Logic RESET SET CT PWM2 PWM1
+
VCORE GATE DRIVER and OUTPUT FETs
OSCILLATOR
COMP
gm Error Amplifier +
FB
VID4 VID3 D/A VID2 VID1 VID0
RL Reference REF Voltage
GND
FIGURE 1. FUNCTIONAL SYSTEM BLOCK DIAGRAM SHOWING MAJOR COMPONENTS
The ISL6560 is a two-power channel, current mode PWM controller with input current sensing. A transconductance error amplifier helps establish the desired droop voltage for microprocessor power supplies and will be explained later. Figure 1 is a functional system block diagram of the IC in a power supply application. A single current sampling resistor, RSENSE, on the input side of the supply monitors the current for both channels via a comparator within the ISL6560. A single comparator insures that both channels are monitored by the same circuitry, helping to balance the operating current of each channel. During normal operation the comparator is tripped by the peak inductor current, terminating the conduction cycle. As more current is needed to supply the output load, the comparator threshold voltage is increased, increasing the inductor current to accommodate the increased load demands.
by the amplifier attempting to make both inputs equal. This does not happen because of the limited loop gain and provides the bases for droop compensation mentioned earlier and described below.
3.0 2.5 VCOMP (Volts) 2.0 1.5 1.0 { 0.5 Output 0 Disable 0 Threshold
/V 5V 12.
20
40
60
80 100 120 VCS(CL) (mV)
140
160
Circuit Operation
Figure 1 will be used to describes operation of the controller. A transconductance error amplifier provides the major voltage control function. The error amplifier's positive input is connected to an internal DAC that is programmed via a 5-bit code from the microprocessor. Regulation is accomplished 6
FIGURE 2. CURRENT COMPARATOR THRESHOLD VOLTAGE AS A FUNCTION OF VCOMP
Figure 2 shows a curve of the current comparator threshold voltage as a function of the error amplifier output voltage, VCOMP. From this curve, it can be seen that as VCOMP
FN9011.3
ISL6560
moves from approximately 1V to 3V, the current comparator threshold voltage ranges from 0mV to 157mV. Also observe as the output load demand increases, driving the inverting input of the error amplifier lower, the output voltage of the error amplifier increases. This voltage increase in VCOMP increases the current comparator threshold voltage to satisfy load demand. Figure 3 is a plot of the oscillator frequency versus timing capacitor value. During supply start-up, or when the error amplifier input is at zero volts, the oscillator's charging current is reduced from its operating value of 150A to 36A, reducing its frequency.
Monitoring and Protection Systems
Power Good
Internal monitoring circuits verify, via a high open drain PWRGD output signal, that the supply voltage is within +124% to -82% of the programed DAC voltage. An external pull-up resistor must be connected from this pin to a positive supply. Load currents should be kept below 100A. Voltages exceeding the above limits will drive the open drain PWRGD pin low. If the output voltage exceeds the 124% limit, the PWM outputs will go low, turning OFF the upper gates and turning ON the lower gates to protect the processor. When the output voltage drops below the limit, normal operation is restored.
Droop Voltage
Gain of the error amplifier is gm x RL. If RL is 10k and the gm is 2.2mS, the gain will be 2.2mS x 10k = 22. For example, assume to satisfy the no-load to full load requirements the VCOMP voltage must increase by 1.5V. The error amplifier input voltage or droop voltage will be 1.5V / 22 = 68mV below the DAC voltage. As will be shown later this is not the sequence one uses when designing a supply, but is useful at this point, to explain the operation.
Initial Voltage
The initial starting, or no-load voltage is set by the programmed DAC voltage and the reference voltage set at the output of the gm amplifier. The reference voltage is connected to the upper end of the amplifier load resistor, RL, shown in Figure 1. Assume that the voltage to the current comparator is set to 1.2V to satisfy the inductor no-load ripple current. This means that the gm amplifier does not have to supply any output current. Under this condition, the error amplifier input is the DAC voltage. Now assume that the reference voltage to the gm amplifier is set to 1.4V, instead of 1.2V. The gm amplifier must reduce its output to 1.2V to set the comparator no-load threshold voltage to the correct voltage to supply the inductor ripple current. The error amplifier output must pull down or reduce the voltage to the comparator by the added 200mV. This will cause the gm amplifier input to go more positive to drive the error amplifier output low. The initial no-load voltage, with a gain of 22, will be 200mV/22 or 9mV high. If the reference voltage is set low by the same amount the no-load starting voltage will be low by that same amount. A 3V reference is provided within the ISL6560. A voltage divider is established by two external series resistors connected between the reference voltage, REF and ground. The center of the two resistors is connected to COMP and sets the initial voltage. The parallel combination sets the equivalent error amplifier load, RL. Determination of the resistor values will be discussed later.
Short Circuit Protection
When a short is placed on the supply, the input supply current exceeds the current comparator maximum level. No more current is available and the output voltage will fall. When the regulator output voltage falls below approximately 375mv, the threshold voltage of the current comparator is limited to 95mV. In addition, the oscillator frequency is reduced. This effectively folds back the available output current to limit load and regulator dissipation.
Supply Disable
The bracketed section on the left hand vertical axis of the curve in of Figure 2 shows a range of voltages that will initiate the disable function within the ISL6560. The PWM outputs are driven low, opening the upper MOSFETs and driving the lower MOSFETs ON. The oscillator is disabled during this time. Connecting an open drain or open collector device or a switch to pull VCOMP to ground will initiate the disable function.
3000 FREQUENCY (kHz)
1000
Oscillator Frequency
An external capacitor establishes the basic timing for the sawtooth oscillator. An internal current source of 150A ramps the timing capacitor from ground to approximately 3V with low values of timing capacitors, (< 150pF). This establishes the basic period for the oscillator. Approximately 150ns is fixed for the retrace. With increasing values of timing capacitors the sawtooth amplitude is reduced because the timing capacitor does not retrace to ground. 7
100
0
50 100 150 200 250 300 350 400 CAPACITOR CT (pF)
450 500
FIGURE 3. OSCILLATOR FREQUENCY vs. TIMING CAPACITOR
FN9011.3
ISL6560 Design Example
This section will highlight a 40A converter, providing the design details for the entire supply. The hardware realization of this design is the ISL6560/62 Evaluation Board. For this example a 40A supply down converting from 12V will be discussed. 5V operation is also viable as an input source. Oscillator frequency is 350kHz, with a channel frequency of 175kHz. The ISL6560 has an internal DAC with VRM 9.0 VID codes. An output voltage of 1.8V, near the maximum output voltage will be used to determine the selection of inductors. Output voltage droop from no-load to full load specification is ~65mv. This sets the effective DC output resistance, (ROUT) to be 65mV/40A = 1.63m. the "K" term is fixed by the input output design criteria.
3.5 L= 3.0 L= 2.5 K (VOLTS) (VIN - VOUT) VOUT fsw x IL VIN K fsw x IL VIN = 10V 2.0 1.5 VIN = 5V 1.0 VIN = 3.3V VIN = 8V
K=
(VIN - VOUT) VOUT VIN
VIN = 12V
0.5
Inductor Selection
Each channel handles half of the 40A output. An inductor ripple current of 40% of the output current or 8A p-p/channel was selected. There is always a compromise between ripple current and regulator performance. Higher values of ripple current, as expected, result in slightly greater dissipation in series pass transistors and losses in other resistive elements in the power path. These disadvantages are offset by improved transient response, with lower values of output capacitors and less output voltage overshoot when the output current is step reduced from heavy load conditions. This overshoot is primarily contributed by the energy stored in the output filter network and is not highly influenced by the control loop. To assist in the selection of the output inductors, two curves are provided. Figure 4 deals with the selection of the voltage terms in the equation: L= (VIN - VOUT) VOUT fsw x IL VIN
0 0 2 4 6 VOUT (VOLTS) 8 10 12
FIGURE 4. "K" AS A FUNCTION OF VOUT FOR FAMILIES OF VIN
2.5 VIN = 12V
2.0 VIN = 8V
K (VOLTS)
1.5
VIN = 10V VIN = 5V
1.0 VIN = 3.3V 0.5
Where: L = inductor value VIN = input voltage VOUT = output voltage or CORE Voltage fsw = oscillator frequency/2 (for each channel) IL= inductor ripple current The (VIN - VOUT) term is the voltage across the inductor and the VOUT/VIN term is the converter duty cycle. The curve of Figure 4 reduces the voltage terms to a single voltage term, "K". To further enhance readability of the curves, the lower portion of Figure 4 was expanded in Figure 5 for output voltages up to only 3.5V. The dotted lines show the selection of an output voltage of 1.8V. With 12V input, K = 1.55V. The curve of Figure 6 shows with the selection of the inductor value. Initially a ripple current of 40% of the full load current was established. Each channel contributes 20A, for a ripple current, IL, of 8A. From this, the value entered into the left-hand axis of Figure 6 is 1.55V/8A = 0.19. With a channel operating frequency of 200kHz, the inductor value will be 900nH, as shown by the dotted lines. This curve shows how you can modify the inductor value by changing the ripple current since
0 0 0.5 1.0 1.5 2.0 VOUT (VOLTS) 2.5 3.0 3.5
FIGURE 5. EXPANSION OF FIGURE 4 FOR VOUT < 3.5V
8
FN9011.3
ISL6560
3 Frequency = Channel fsw
Hz 2M 1M
1
(VOLTS)
Hz Hz 0 20 z kH 0k Hz
(Amps)
0k 50
high peak currents can cause heating of these capacitors and can result in premature failure if not properly designed. The value of the RMS current that these capacitors must share can be approximated with the aid of the curve of Figure 7. The dotted lines show determination of the current multiplier. For the 40A design with the 1.8V/12V = 0.15 duty cycle, the RMS current is 0.24 x 40A = 9.6A. From this curve, it is evident that the maximum current is only 10A. If the duty cycle was 50%, each channel would be ON for its full cycle and the ripple would go to zero.
0.3
K IL
10
0.1
CURRENT MULTIPLIER
0.01 100nH
0.2
1H Inductance
10H
FIGURE 6. INDUCTOR SELECTION CURVES
0.1
These curves help to visualize that in some cases, major changes in some parameters only result in subtle changes in other parameters. For example, going from 175kHz to the 200kHz channel frequency.
0 0 0.1 0.2 0.3 0.4 0.5 DUTY CYCLE (VO/VIN)
Output Capacitors
The combined series resistance and inductance of the output capacitors is one of the limiting factors in the supply's response to transient loads. Most DC/DC converters do not have the bandwidth or operating frequency to respond to rapid load changes. Therefore, attention must be paid to the filter network, for it must be the major source of energy during step load changes. The output capacitors must respond by supplying the initial load current, until the regulator loop responds and the inductor current slews. Bulk capacitors store energy, but are limited by the effective series resistance and inductance path to their reservoir of energy. Considering only the series resistance, the total effective series resistance of the parallel connected capacitors should be equal to or less than the effective DC ROUT of the supply. As mentioned earlier ROUT is approximately 1.63m. For this example, six 1500F, 4V Sanyo OS-CON capacitors provide a maximum ESR of 1.66m, roughly meeting the design target. To a first order, output ripple voltage is the product of the capacitor's ESR and the ripple current. In this design it is 1.66m x 8A = 13.3mV. Sixteen 22F ceramic capacitors help provide highfrequency bypassing by providing lower inductance and low high-frequency impedance. It is essential that additional ceramic capacitors also be place at the load to help stabilize the load voltage and minimize additional droop at the load.
FIGURE 7. CURRENT MULTIPLIER vs. DUTY CYCLE
Rubycon ZA series capacitors were selected for the input capacitors. Their 470F, 16V capacitors have a maximum RMS current rating of 1.6A at 105oC ambient. For 9.6A, six capacitors are required. On any switching supply, high frequency decoupling may be necessary on the supply input to keep the high peak current, fast rise current pulses contained within the supply. Often a small inductor is placed in series with the input line to help reduce this potential source of EMI. Ceramic capacitors to ground also help lower the high frequency impedance to shunt the high frequency components to reduce and contain the high speed current pulses.
RSENSE Selection
Each channel supplies a current of 20A. Add the 4A ripple (half of the ripple current) component and the minimum voltage across the current sense resistor that will trip the comparator is the minimum limit of 142mV. The RSENSE resistor value is then 142mV / 28A = 5.07m. A 5m resistor was used for this function to insure the minimum current. The maximum current is also important. The maximum threshold voltage for the current comparator is 172mV. The maximum current would be: 172mV / 5m = 34.4A per channel. The 4A of ripple current per channel must be subtracted to yield 30.4A per channel. The maximum output current would be two times the channel current, or 60.8A.
Input Capacitors
The input capacitors are also critical to supply operation. They must provide enough energy to prevent the input voltage from dropping due to load transients. In addition, the 9
FN9011.3
ISL6560
To calculate the dissipation in the 5m resistor, we used only half of the ripple current, 4A, to give a nominal dissipation of:
1.8V I RMS = Ip D = Ip -----------12V
2 2 * Power = Ip x D x R SENSE = 3 0.4 x 0.15 x 5m
Once the value for RL is set, only the values of the resistors that make up the voltage divider must be determined. Figure 8 shows the equations to determine the resistor network that makes up RL.
VREF = 3V
Power = 0.69W per channel or 1.38W for both channels
RU
R U || R B = R L I RIPPLE x R SENSE x ni V SET = 1V + --------------------------------------------------------------2
To COMP pin, this voltage is VSET
Where IP is the peak current and D is the duty cycle. Two 10m, 1W resistors in parallel were selected.
RB
V REF R U = -------------- x R L V SET
3V R U = --------------- x 8.7k = 20.9k 1.25V
RL Selection
As discussed in the section under Droop Voltage and shown in Figure 1, resistor RL establishes the gain of the transconductance error amplifier. It is this resistor that sets the droop voltage or regulation. Like any feedback system, the higher the gain the better the regulation. The value of this resistor may be determined from the following equation:
ni x R SENSE 12.5 x 5m R L = ---------------------------------------- = ------------------------------------------------------- = 8.7k 2.2mS x 1.63m x 2 gm x R OUT x 2 gm Amplifier Gain = gmAmplifierGain = gm x RL = 2.2mS x 8.7k = 19.1
V SET R B = ------------------------------------ x R U V REF - V SET 1.25V R B = ----------------------------- x 20.9k = 14.9k 3V - 1.25V FIGURE 8. EQUATIONS TO DETERMINE RL DIVIDER
CC and RC Selection
Optimum transient response depends upon the selection of the compensation capacitor network placed across the output of the transconductance error amplifier. To a first order, the selection of the capacitor, CC, placed across the error amplifier may be determined by making the product of the regulator output resistance and output capacitors equal to the product of the RL and CC. This yields the equation for the compensation capacitor:
R OUT x C OUT 1.63m x 9mF C C = -------------------------------------- = ---------------------------------------- = 1.68nF 8.7k RL
The ni term is the ratio of the VCOMP to the current comparator threshold voltage; see Figure 2. RL is made up of two resistors that form a voltage divider from the internal 3V reference supply. As described earlier in the Circuit Description section, the output voltage of the gm amplifier establishes the threshold voltage of the current comparator. At approximately 1V, the current comparator threshold voltage is near zero. With no current demands, the regulator output voltage would be the same as the programmed DAC voltage. However, an 8A ripple current was selected for this design. This results in the output of the gm amplifier moving upwards to supply the ripple current. The voltage at the COMP pin, VSET, will be:
I RIPPLE x R SENSE x ni V SET = 1V + --------------------------------------------------------------2 8A x 5m x 12.5 = 1V + --------------------------------------------- = 1V + 250mV = 1.25V 2
The voltage divider establishes the reference voltage for VCOMP that was set to 1.2V for this design, so the error amplifier must drive the COMP pin 50mV more positive to bring it to 1.25V from the 1.2V originally set. This additional 50mV output will result in an input voltage to the error amplifier of: 50mv / 19.1 = 2.62mV below the programmed DAC voltage of 1.8V. Neglected, is a negative term associated with the 60ns delay of the current comparator. This delay will cause the current ramp to be slightly greater than predicted by the equation. This means that the initial setting should be slightly reduced to account for the increase in current.
A 1nF capacitor was selected from transient testing. To prevent excessive phase shift due to the compensation capacitor, it is usually necessary to place a resistor inseries with the capacitor to prevent excessive phase shift beyond the frequency of interest. This is pole cancellation and the resistor is approximately 0.5 x RL. Figure 9 shows this network and the equivalent circuit is approximately 0.5 x RL. Many variables have been used in the selection of the various gain and filter networks to this point. A broad range of component tolerances range from 1% to 20% have been used in the design. Therefore, it is important to evaluate the entire system with dynamic pulse load testing. This will verify optimum transient response and also indicate poor response in terms of excessive overshoot, ringing or oscillation if the compensation network is not optimum.
VREF = 3V AC Equivalent RU CC RC CC RC RL
To COMP pin RB
RC = 0.5 x RL
FIGURE 9. COMPENSATION CIRCUIT
10
FN9011.3
ISL6560
MOSFET Selection and Considerations
In high-current PWM applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors. The power dissipation includes two loss components; conduction loss and switching loss. These losses are distributed between the upper and lower MOSFETs according to duty factor (see the following equations). The conduction losses are the main component of power dissipation for the lower MOSFETs, Q2 and Q4 of Figure 10. Only the upper MOSFETs, Q1 and Q3 have significant switching losses, since the lower device turns on and off into near-zero voltage. The equations assume linear voltage-current transitions and do not model power loss due to the reverse-recovery of the lower MOSFET's body diode. The gate-charge losses are dissipated by the driver IC and don't heat the MOSFETs. However, large gate-charge increases the switching time, tSW which increases the upper MOSFET switching losses.
L3 12V +VIN 1H 2 - 4.7F C41-42 10 R6 4.7F C40 1 VID4 INPUT VID CODES from PROCSSOR { { 22k R11 1nF C12 15k R12 4.3k R27 1k R5 2 VID3 3 VID2 4 VID1 5 VID0 6 COMP 7 FB 8 CT VCC 16 REF 15 CS- 14 PWM1 13 PWM2 12 CS+ 11 PWRGD 10 GND 9 1nF C10 330pF C11 5m R13 20 R14 15nF C20 R7 330 0.1F 1 UGATE PHASE 8 2 BOOT 3 PWM 4 GND PVCC 7 900nH VCC 6 LGATE 5 1F C2 C21, C24-28 6 - 1200F +VCORE Q2 HUF76145 C1 L1 Q1 HUF76139
Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. A separate heat sink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow.
I O x r DS ( ON ) x V OUT I O x V IN x t SW x F S P UPPER = ----------------------------------------------------------- + ---------------------------------------------------V IN 2 I O x r DS ( ON ) x ( V IN - V OUT ) P LOWER = -------------------------------------------------------------------------------V IN
2 2
Figure 10 shows a schematic of the circuit developed from the proceeding computations. This circuit is implemented on the ISL6560/62 Evaluation Board. The next section will discuss PC board layout.
6 - 470F C15, C17-18, C29, C50-51
HIP6601ECB
150pF ISL6560 C14 100pF C13 0.1F 1 UGATE PHASE 8 2 BOOT 3 PWM 4 GND PVCC 7 VCC 6 LGATE 5 1F C4 C3
Q3 HUF76139 L2 900nH Q4 HUF76145 16 - 22F C19, C30, C34-37, C39, C45-49, C60-63
HIP6601ECB
FIGURE 10. SCHEMATIC DIAGRAM OF A 40A SUPPLY USING THE ISL6560 CONTROLLER AND HIP6601 GATE DRIVERS
PC Board Layout Considerations
Like all high-current supplies where low-voltage control signals in the millivolt range must live with high voltage and high-current switching signals, PC board layout becomes crucial in obtaining a satisfactory supply. Figure 11 shows a simplified diagram of the critical areas of a PC board layout. This diagram and the following material represent goals to work towards during the layout phase. Goals will be compromised during the layout process due to 11
component placement and space constraints. The following text reviews these layout considerations in more detail.
Current Sampling
1. Place the current sampling or sense resistor as close as possible to the upper MOSFET drains. This is important since the added inductance and resistance increase the impedance and result in a reduction in drain voltage during high peak pulse currents.
FN9011.3
ISL6560
2. Current sense is critical, especially at lower current levels where the current comparator threshold voltage is lower. A good Kelvin connection requires that the voltage sample must be taken at the RSENSE resistor ends, and not at the planes to which the resistor is connected. 3. The lines to the current sense resistor should be parallel and run away from the PHASE or PWM signals to prevent coupling of spikes to the current comparator input that may delay or advance triggering of the comparator. Parallel routing will work towards equal exposure for both lines, so that the comparator common mode rejection characteristic will reduce the influence of coupled noise. 4. Place the current sense filter network near the controller. This will help reduce extraneous inputs to the comparator. 5. Make sure the DC plus pulse voltage inputs to the current sense comparator, CS+ and CS-, do not exceed the voltage on the VCC pin by more than the specified limit of VCC + 0.3V. 2. The two voltage sampling lines described in item 1 above should also be routed away from any high-current or highpulse voltages such as the phase lines or pads. Doing this will reduce the possibility of coupling undesired pulses into the feedback signal and either modifying the output of the error amplifier or, if of sufficient amplitude, spuriously triggering the current comparator by readjusting the threshold voltage.
Other Considerations
1. Keep the leads to the timing capacitor connected to pin CT short and return the ground directly to Pin 9. 2. When using a transistor to disable the converter by pulling the CT pin to ground, place the transistor close to the CT pin to minimize extraneous signal pickup. 3. As in all designs, keep decoupling networks near the pins that must be decoupled. For example, the decoupling/filter network on the FB input. The series resistor should be located next to the FB pin. 4. Large power and ground planes are critical to keeping performance and efficiency high. Consider a 1m resistance in a 40A supply line. With 1.8V output, this results in slightly over 2% power loss in the 72W supply.
Voltage Sampling
1. To obtain optimum regulation use the Kelvin connection for the input voltage sample as shown in Figure 11. The ground connection, Pin 9 of the ISL6560 should be connected to the system ground at the load.
12V +VIN
Keep Leads Together & Away from Output
Place Near Drains of the Output Transistors
1 VID4 Input VID Codes from Processor { { 2 VID3 3 VID2 4 VID1 5 VID0 6 COMP 7 FB 8 CT
VCC 16 REF 15 CS- 14 PWM1 13 PWM2 12 CS+ 11 PWRGD 10 GND 9 Locate Parts Next to IC 1 UGATE PHASE 8 2 BOOT 3 PWM 4 GND PVCC 7 VCC 6 LGATE 5 +VCORE
HIP6601ECB
ISL6560 Locate Parts Next to IC
Try to return bypass capacitors to ground of lower MOSFETs
FIGURE 11. SCHEMATIC DIAGRAM SHOWING ONLY ONE CHANNEL OF `IDEAL' COMPONENT PLACEMENT
12
FN9011.3
ISL6560 ISL6560 Supply Design Sequence
Please note several changes from the computations in the body of the data sheet. An operating frequency of 400kHz was chosen. A 15mV offset voltage was added to the noload output voltage to show the design procedure. F. Output Capacitors:
Capacitor ESR R OUT = 1.63m Sanyo 1500F, 4V OS-CON Capacitors have an ESR < 10m Six capacitors < 1.66m Total Capacitance = 9mF
ISL6560 Supply Design Sequence
A. Specifications:
Output Current: Input Voltage: 40A 12V
G. Input Capacitor's RMS Current:
Use the curve of Figure B. CURRENT MULTIPLIER
0.3
Output Voltage: VDAC + 15mV Output Voltage for Calculations: VDAC = 1.8V + 15mV Droop Voltage: 65mV Oscillator Frequency: 400kHz (fSW)
0.2
0.1
0 0 0.1 0.2 0.3 DUTY CYCLE (VO / VIN) 0.4 0.5
B. Calculate ROUT:
V DROOP 65mV R OUT = ----------------------- = --------------- = 1.63m I OUT 40A
FIGURE B. CURRENT MULTIPLIER vs. DUTY CYCLE
G. Input Capacitor's RMS Current: (continued) C. Determine Frequency Setting Capacitor CT:
From curve of Figure A, for 400kHz use 120pF.
3000
For 40A with a duty cycle (D) of: V OUT 1.8V D = --------------- = ----------- = 0.15 V IN 12V The multiplier from Figure B is 0.24. I RMS = 0.24 x 40A = 9.6A
FREQUENCY (kHz)
1000
Panasonic 470F, 16V Rubycon ZA series capacitors have a RMS current rating of 1.6A. Six capacitors were selected.
100
0
50 100 150 200 250 300 350 400 CAPACITOR CT (pF)
450 500
H. Current Sense Resistor (RSENSE):
V CS ( TH )MIN 142mV R SENSE = ----------------------------------------- = ------------------------ = 5.07m 20A + 8A I OUT I RIPPLE ------------ + --------------------2 2 Use a 5m resistor
FIGURE A. OSCILLATOR FREQUENCY vs. TIMING CAPACITOR
D. Select Inductor Ripple Current (IL):
Choose 40% of IOUT: I L = 40A x 0.4 = 16A Or 8A / Channel
I. RSENSE Dissipation:
I RMS = I PEAK D Power = I 2 P x D x R SENSE (Using half the ripple current)
Where: IP = 34.4A -4A = 30.4A
E. Determine the Inductors:
V IN - V OUT V OUT 12V - 1.8V 1.8V L = --------------------------------- x ----------------- = ----------------------------------- x -----------f SW V IN 200kHz x 8A 12V ----------- x I L 2 = 956nH
Power = 30.4A x 0.15 x 5m Power = 0.69W per channel or 1.38W for both channels Used two 10m, 1W resistors in parallel.
2
J. RL Selection:
R L ni x R SENSE 12.5 x 5m = ---------------------------------------- = ------------------------------------------------------- = 8.7k 2.2mS x 1.63m x 2 gm x R OUT x 2
gm Amplifier Gain = gm x RL = 2.2mS x 8.7k = 19.1
13
FN9011.3
ISL6560 Small Outline Plastic Packages (SOIC)
N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA h x 45o 0.25(0.010) M BM
M16.15 (JEDEC MS-012-AC ISSUE C) 16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES SYMBOL A A1 B MIN 0.053 0.004 0.014 0.007 0.386 0.150 MAX 0.069 0.010 0.019 0.010 0.394 0.157 MILLIMETERS MIN 1.35 0.10 0.35 0.19 9.80 3.80 MAX 1.75 0.25 0.49 0.25 10.00 4.00 NOTES 9 3 4 5 6 7 8o Rev. 1 02/02
L
C D E e H h
C
0.050 BSC 0.228 0.010 0.016 16 0o 8o 0.244 0.020 0.050
1.27 BSC 5.80 0.25 0.40 16 0o 6.20 0.50 1.27
e
B 0.25(0.010) M C AM BS

A1 0.10(0.004)
L N
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 14
FN9011.3

▲Up To Search▲

Price & Availability of ISL6560

	To Download ISL6560 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .